Wireless Prototyping and Production Development Essentials
How teams work together to iterate quickly, increase efficiency with proven design IP, and automate RTL code and verification model creation
An 8-minute read
Section 1
Top-Down Collaboration
Bring together multiple skill sets early in the process
With the growth of wireless standards and infrastructure, new systems and hardware must be developed under a rapid timeline. Traditional workflows that divide responsibilities and rely on specification documents prevent the type of multidiscipline collaboration needed to deliver novel products on schedule.
Click the numbers on the image below to see how engineering teams can collaborate.
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A Multidomain Design Platform
Bring together system, algorithm, and domain-specific engineers to collaborate in a visual environment to explore and develop the system, algorithms, and architecture together. You can model your antenna, receiver, amplifiers, ADC/DAC, modulation/demodulation, error correction, and signal processing, along with core math and logic.
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System-Level Simulation for Validation and Verification
Simulate the entire system from antenna to bits to optimize system throughput and to detect and eliminate costly issues early. The higher level of abstraction means that there are fewer details to simulate, which results in faster run time and easier debugging. Manage tests and track functional coverage to ensure robust verification before prototyping and production development.
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The Ability to Refine the Implementation Architecture
This top-down approach enables communications, DSP, and hardware engineers to continuously collaborate to adapt algorithms to work on a stream of bits, trade off parallel processing versus resource usage, manage the timing and latency of data flow, and balance numerical accuracy versus the efficiency of fixed-point quantization. They can simulate each refinement step using the same stimulus as algorithm design, while comparing results and performance against the algorithm.
A Multidomain Design Platform
Bring together system, algorithm, and domain-specific engineers to collaborate in a visual environment to explore and develop the system, algorithms, and architecture together. You can model your antenna, receiver, amplifiers, ADC/DAC, modulation/demodulation, error correction, and signal processing, along with core math and logic.
System-Level Simulation for Validation and Verification
Simulate the entire system from antenna to bits to optimize system throughput and to detect and eliminate costly issues early. The higher level of abstraction means that there are fewer details to simulate, which results in faster run time and easier debugging. Manage tests and track functional coverage to ensure robust verification before prototyping and production development.
The Ability to Refine the Implementation Architecture
This top-down approach enables communications, DSP, and hardware engineers to continuously collaborate to adapt algorithms to work on a stream of bits, trade off parallel processing versus resource usage, manage the timing and latency of data flow, and balance numerical accuracy versus the efficiency of fixed-point quantization. They can simulate each refinement step using the same stimulus as algorithm design, while comparing results and performance against the algorithm.
Key Takeaways
- Enable collaboration between multiple domain experts
- Simulate system-level behavior to detect and eliminate costly issues early
- Improve quality through broader architecture exploration
Learn More About Model-Based Design
Adopting Model-Based Design for FPGA, ASIC, and SoC Development
Section 2
FPGA Prototyping Without VHDL/Verilog Expertise
Target and debug FPGA prototype hardware directly from MATLAB and Simulink
Prototyping wireless communications algorithms on FPGA or software-defined radio (SDR) hardware platforms delivers early insight to performance in realistic operating conditions, and often serves as a key demonstration checkpoint as the project progresses toward production development. Where traditional prototyping workflows place a heavy burden on scarce hardware design engineers, using MATLAB® and Simulink® enables communications and DSP engineers to be more self-sufficient in creating and debugging FPGA prototypes. This approach results in faster iterations and getting to a working prototype with less time and effort.
Incremental Prototype
Guided and Automated Hardware Targeting
While there are no shortcuts to targeting FPGA hardware, guidance and automation make it more attainable. Fixed-Point Designer™ automates the quantization process to help you balance efficiency versus accuracy. The HDL Coder workflow advisor manages the process from helping prepare your design for targeting all the way through FPGA implementation.
Connected Analysis and Debug
Prototyping introduces unanticipated real-world effects such as interference, which can cause the design to malfunction or perform more poorly than expected. You can use MATLAB and Simulink to analyze and debug these issues with the device connected directly or by capturing the over-the-air waveforms to use in simulation.
“Implementing this project took 9 months with four people. In our estimation we saved about 50–70% of the time versus starting without MATLAB involvement and hand-writing Verilog or VHDL code.” – Mikhail Galeev,
Key Takeaways
- Iterate and get to a working prototype more quickly
- Increase your capability to prototype on digital hardware
- Analyze and debug from within MATLAB and Simulink
Request a Demo or Free Trial
Try HDL Coder for your next project prototyping on FPGA-based development kits.
Section 3
Hardware-Proven Design IP
Speed your project schedule by using configurable hardware implementations of standards-based algorithms
Wireless communications rely heavily upon standard signal protocols, modulation/demodulation schemes, and error correction coding to ensure system and device interoperability. In most cases, this standard functionality does not differentiate your application, but you still need to integrate it into your FPGA or ASIC. Using proven intellectual property (IP) saves your engineers' time and effort so they can focus on developing and implementing your unique functionality.
- 1. Reference Applications
- 2. IP Blocks
- 3. Top-Down Verification Workflow
Key Takeaways
- Save hardware design and verification time and effort by using proven IP
- Focus your hardware engineering resources on your unique functionality
- Verify, adjust, and generate code from high-abstraction wireless design IP
Learn More About Design IP
Explore the reference applications and design IP blocks in Wireless HDL Toolbox.
Section 4
Code Generation for Hardware Design and Verification
Explore and simulate hardware architecture, then automatically generate project-specific RTL and verification components
Relying on specification documents to communicate functional intent exposes risks from oversights and assumptions and makes it difficult to adapt to changes. A top-down workflow refines the high-level algorithms with hardware implementation architecture, enabling easy exploration of more options, followed by high-level verification. From there you can directly generate code and models to begin production hardware design and verification.
Collaboration Between Algorithm and Hardware Engineers
Hardware engineers can collaborate with communications and DSP engineers in a visual environment to adapt their algorithms with parallelism, timing, and fixed-point quantization to map efficiently to hardware while producing sufficiently accurate results. The result is an easy-to-follow simulation model from which you can generate code for downstream design and verification.
Target-Independent HDL Code Generation
After iterative refinement from algorithm to fixed-point hardware architecture, you can automatically generate readable and synthesizable VHDL® or Verilog® RTL. Customize the RTL for your project requirements and target device and adapt to changes with agility.
SystemVerilog Verification Component Generation
You can start connecting algorithm and hardware development by generating SystemVerilog DPI or UVM verification components from MATLAB or Simulink algorithms and tests. Automatic verification model generation enables changes in the digital algorithms to be quickly updated for simulation in analog implementation, and vice versa.
“We have improved communication between teams, reduced development time, and reduced risk by evaluating system performance early in the design process.” –
Key Takeaways
- Improve quality by exploring a broad range of hardware architecture options
- Quickly adapt to changes and re-generate code for new requirements
- Generate models to speed verification environment creation