How teams work together to iterate quickly, increase efficiency with proven design IP, and automate RTL code and verification model creation
Bring together system, algorithm, and domain-specific engineers to collaborate in a visual environment to explore and develop the system, algorithms, and architecture together. You can model your antenna, receiver, amplifiers, ADC/DAC, modulation/demodulation, error correction, and signal processing, along with core math and logic.
Simulate the entire system from antenna to bits to optimize system throughput and to detect and eliminate costly issues early. The higher level of abstraction means that there are fewer details to simulate, which results in faster run time and easier debugging. Manage tests and track functional coverage to ensure robust verification before prototyping and production development.
This top-down approach enables communications, DSP, and hardware engineers to continuously collaborate to adapt algorithms to work on a stream of bits, trade off parallel processing versus resource usage, manage the timing and latency of data flow, and balance numerical accuracy versus the efficiency of fixed-point quantization. They can simulate each refinement step using the same stimulus as algorithm design, while comparing results and performance against the algorithm.
Bring together system, algorithm, and domain-specific engineers to collaborate in a visual environment to explore and develop the system, algorithms, and architecture together. You can model your antenna, receiver, amplifiers, ADC/DAC, modulation/demodulation, error correction, and signal processing, along with core math and logic.
Simulate the entire system from antenna to bits to optimize system throughput and to detect and eliminate costly issues early. The higher level of abstraction means that there are fewer details to simulate, which results in faster run time and easier debugging. Manage tests and track functional coverage to ensure robust verification before prototyping and production development.
This top-down approach enables communications, DSP, and hardware engineers to continuously collaborate to adapt algorithms to work on a stream of bits, trade off parallel processing versus resource usage, manage the timing and latency of data flow, and balance numerical accuracy versus the efficiency of fixed-point quantization. They can simulate each refinement step using the same stimulus as algorithm design, while comparing results and performance against the algorithm.
Adopting Model-Based Design for FPGA, ASIC, and SoC Development
While there are no shortcuts to targeting FPGA hardware, guidance and automation make it more attainable. Fixed-Point Designer™ automates the quantization process to help you balance efficiency versus accuracy. The HDL Coder workflow advisor manages the process from helping prepare your design for targeting all the way through FPGA implementation.
Prototyping introduces unanticipated real-world effects such as interference, which can cause the design to malfunction or perform more poorly than expected. You can use MATLAB and Simulink to analyze and debug these issues with the device connected directly or by capturing the over-the-air waveforms to use in simulation.
“Implementing this project took 9 months with four people. In our estimation we saved about 50–70% of the time versus starting without MATLAB involvement and hand-writing Verilog or VHDL code.” – Mikhail Galeev,
Hardware engineers can collaborate with communications and DSP engineers in a visual environment to adapt their algorithms with parallelism, timing, and fixed-point quantization to map efficiently to hardware while producing sufficiently accurate results. The result is an easy-to-follow simulation model from which you can generate code for downstream design and verification.
After iterative refinement from algorithm to fixed-point hardware architecture, you can automatically generate readable and synthesizable VHDL® or Verilog® RTL. Customize the RTL for your project requirements and target device and adapt to changes with agility.
You can start connecting algorithm and hardware development by generating SystemVerilog DPI or UVM verification components from MATLAB or Simulink algorithms and tests. Automatic verification model generation enables changes in the digital algorithms to be quickly updated for simulation in analog implementation, and vice versa.
“We have improved communication between teams, reduced development time, and reduced risk by evaluating system performance early in the design process.” –